This invention relates to equalization circuits. More particularly, this invention relates to equalization circuits that have programmable differential capacitance to improve performance.
Known equalization circuits often employ capacitance devices to improve signal transition speed and strength when responding to the transition of an incoming signal. Equalization circuits are typically used with differential signaling (such as low voltage differential signaling (LVDS) or current mode logic (CML) signaling). Differential signals are pairs of signals that propagate in parallel. Each is usually a logical complement of the other. That is, when one signal is at a high voltage (e.g., a “logical 1”), the other is at a low voltage (e.g., a “logical 0”), and vice versa. The equalization circuit operates on both signals substantially simultaneously.
Differential signals (e.g., V1 and V2) can be equivalently thought of as a difference signal (i.e., V1−V2) and a common mode signal (i.e., ½(V1+V2)). Similarly, any gain provided by the equalization circuit to the two signals (e.g., A1 and A2) can be equivalently thought of as a difference gain (Ad=½(A1−A2)) and a common mode gain (Ac=A1+A2)). The relative sensitivity of a circuit to a difference signal as compared to a common mode signal is known as the common-mode rejection ratio (CMRR=Ad/Ac). Many circuits are required to respond precisely to the difference signal. Such circuits should have a high CMRR (i.e., low common mode signal gain/high common mode signal rejection). This will at least lessen, if not eliminate, the adverse effects of common mode signal noise.
Known equalization circuits, however, may have the disadvantage of relatively poor common mode signal noise rejection, resulting in a low CMRR. A low CMRR can result in data errors (e.g., a logical 0 being incorrectly interpreted as logical 1 and/or vice versa). Such errors can adversely affect an entire system.